Responsibilities

• Lead the integration of complex RTL blocks and IPs into large-scale SoCs for AI cloud systems and data centers.
• Own and maintain the Front-end environment, integration TFM and data basesDefine and implement chip- and subsystem-level integration architecture from concept to production.
• Perform RTL quality checks (Lint, CDC/RDC, power-aware verification, synthesis readiness).
• Drive integration flows for clock, reset, power domains, and interconnect fabrics.
• Collaborate with cross-functional teams including architecture, RTL design, verification, physical design, DFT, and software.
• Contribute to the design of highly innovative Switch and NIC products by ensuring seamless RTL integration.
• Act as a key contributor in shaping the integration methodologies and infrastructure of the new Israeli site.

Requirements:

• 12+ years of hands-on experience in RTL integration and front-end flows (SystemVerilog/Verilog).
• B.Sc. in Electrical Engineering, Computer Engineering, or a related field – required.
• M.Sc. or Ph.D. – an advantage.
• Proven track record in SoC integration and sign-off for high-performance, scalable digital systems.
• Background in networking architectures and IPs (Switches, NICs, SmartNICs).
• Relevant knowledge in networking functions such as packet processing, RDMA, Ethernet SerDes, PCIe switching, and MAC design.
• Solid experience with integration checks, synthesis flows, and low-power methodologies.
• Strong leadership skills and ability to drive complex integration projects independently.
• Excellent communication skills and fluency in English.